1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device, a method for forming an alignment mark, and a semiconductor device, and particularly relates to a technology by which, even when an alignment mark is large in size, its abnormal oxidation can be prevented.
2. Related Art
Alignment of a wafer and a photomask is an essential step in a process for manufacturing a semiconductor device, and it is required to suppress an error that may be generated in the alignment step to the minimum. In order to correctly superpose a pattern to be successively formed on a pattern provided on a wafer, alignment marks are used (for example, Japanese laid-open patent applications, JP-A-2002-373974, JP-A-2005-142252, JP-A-2004-39731 describe examples of related art). There are many alignment marks in a variety of shapes and sizes, and most of them are in a rectangular form as viewed in a plan view, and has sides that are several μm to several ten μm in length, as exemplified by the following marks A-D:
Mark A: 3 μm in length×4 μm in width
Mark B: 4 μm in length×4 μm in width
Mark C: 6 μm in length×72 μm in width
Mark D: 15-25 μm in length×15-25 μm in width
When a plug electrode is formed on a semiconductor substrate, a via hole (also called a “contact hole”) is formed in an interlayer dielectric film, and an opening section for an alignment mark is formed at a position separated from the via hole. Then a tungsten (W) film is formed on the interlayer dielectric film, thereby embedding the via hole with the W film. The W film is formed by a CVD (chemical vapor deposition) method. Then, CMP (chemical mechanical polishing) is applied to the entire upper surface of the semiconductor substrate to remove the W film on the interlayer dielectric film, whereby the plug electrode and the alignment mark are completed.
The alignment mark has a unit pattern size of several μm square or greater, which is larger than a pattern (<1 μm) that is used in an actual circuit, such that a step difference is formed in the surface of the W film that composes the alignment mark. In other words, in a CVD method, the smaller the diameter of a hole, the quicker the hole tends to be embedded, such that embedding of the via hole is completed before the opening section is completely embedded by the W film. When the opening section is actually used as an alignment mark, the incompletely embedded opening section would not particularly cause a problem because the opening section cannot be recognized as a mark without a step difference being present to some degree.
However, in a process for manufacturing a ferroelectric memory (FeRAM: ferroelectric RAM), after a plug electrode and an alignment mark are formed, an oxidation barrier film is formed over them, and a high-temperature heat treatment is conducted. At this time, as shown in FIG. 3, if a step difference at an alignment mark is too deep (large), the coverage of an oxidation barrier film 91 in an opening section H′ is reduced (in other words, the oxidation barrier film 91 would have locally thin portions, such as, portions circled by dotted lines in FIG. 3). As a result, the required barrier property of the oxidation barrier film 91 is lost, which causes a problem in that a W film 93 inside the opening section H′ becomes abnormally oxidized.
When the W film 93 is abnormally oxidized, its volume expands (in other words, the alignment mark expands), which leads to a possibility that the accuracy in aligning the wafer and photomask in steps after the high-temperature treatment may lower. Also, the expanded oxide may be scattered over the wafer surface, and may remain as particles.